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ONNX op wishlist: typed Where, pair compares, copy-free matmul_f32, gather_rows_f32, float accumulation order - #400
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…Where); one generic body for the blend family Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
…and i64 scalar compares ONNX Equal/Less/Greater take two tensors. i64 compares go through U64x8 cmpgt/cmpeq with the sign bit flipped, which every backend has. Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
…king, no result buffer); matmul_f32_batched Same matrixmultiply kernel, bit-identical to the packed path on row-major, column-major, transposed, stepped and reversed inputs. Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
…ws) index rule, refusing instead of panicking Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
…ce/polarity plane, not a sign plane Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
…ype_complexity) Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
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… comparing CPU tiers Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
sum/mean_axis are bit-identical on AVX-512, FMA+AVX2, AVX, SSE2 and NEON (fixed eight-way order); gemm_f32 splits into an FMA class and a non-FMA class with the same k order. Both facts are pinned by tests. Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
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Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
…f32_batched validates inner shapes even for an empty batch Both from the Codex review on #400. On 64-bit the fixture values are unchanged, so the pinned gemm hash still holds. Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
Records #402, plus the rows #400 and #401 moved. New dots N22-N26: the adders as facade words with no consumer yet, the exp speed-up reaching every exp-based word, AVX2 select mask packing as a second array-backed cost, NEON scalar fcmp/csel in simd_exp_f32, and the transactional Abacus against the non-transactional eager counter. Fruit L20, L21, H12, H13; PR C not planned. Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
This adds the ndarray functions that lance-graph's ONNX registry probe asked for in its wishlist. That is D-TRACT-HARVEST-0; on Jina v5 small, 3,474 of 7,620 nodes are still unregistered. Each item was first checked against master to confirm it was a real gap. This session pushes to one branch only, so the items come as one commit each rather than one PR each.
1. A typed
Where:blend_f32,blend_f32_scalar,blend_i64,blend_i64_scalarblend_i32. The select moves whole elements and never computes on them, so f32 NaN payloads and-0.0come through bit for bit; the test checks both.Where(mask, scores, -inf)without filling a-infvector.2. Comparing two arrays into a mask, plus i64 compares
{eq,lt,le,gt,ge}_{f32,i32,i64}_pair_to_mask(a, b, out)cover ONNXEqual,Less,Greaterand the rest. The f32 versions follow IEEE rules, so NaN compares false.{eq,ne,lt,le,gt,ge}_i64_to_mask, comparing an i64 array against a scalar. No backend has a signed i64 compare, so these go throughU64x8::cmpgt_mask/cmpeq_maskafter XOR-ing the sign bit, which maps signed order onto unsigned order exactly.MIN/MAX, ±0, ±inf and NaN.3.
matmul_f32without copies, andmatmul_f32_batchedmatmul_f32used to make two packing copies and allocate a result buffer. It now callsmatrixmultiply::sgemm, the same kernel, with each view's own strides, and writes straight intoout.outis overwritten without being read, andk = 0gives zeros.outmust still be row-major: the existingNonContiguousOutputcheck is unchanged.matmul_f32_batchedtakes[b,m,k] × [b,k,n]. Arhswith batch size 1 is shared by every entry; any other batch-size mismatch is refused.4. Float accumulation order across CPU tiers
examples/float_accum_probe.rshashes the bits of a fixedgemm_f32and a fixedmean_axis/sum. I ran it on five tiers, using qemu-cputo choose matrixmultiply's kernel:sum,mean_axisgemm_f32sumandmean_axisgive the same bits on every tier. They use a fixed eight-way partial-sum order, which is written in Rust source, with no FMA and no reassociation.gemm_f32gives two sets of results, not five. The FMA kernels agree with each other across x86 and ARM, and so do the non-FMA kernels. The order overkis therefore the same in all five; only fused versus separate rounding differs..claude/knowledge/float-accumulation-order.md.5.
hpc::gather::gather_rows_f32[-rows, rows). A bad index returnsGatherErrorinstead of panicking or clamping.outis unchanged on an error.Also: the
simd_stridemodule doc now nameslut9's second input as the DR512 presence/polarity plane, not a sign plane.Evidence
config-v3): 14/14.cargo clippy --features std --all-targets -- -D warningsandcargo fmtare clean, the new doctests pass, and the facet-stride guard is clean on the diff.cargo checkfor wasm32 fails ingetrandomon master as well.🤖 Generated with Claude Code
https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY