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D-SIMD-MICRO-MACRO-1 step 1: packed microtile oracle (lab fixture) - #406
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One 128-bit tile carrying 5xU24/I24 (+8 metadata bits) or 14xU9/I9 (+2 spare) isolated fields: wrapping add/sub, per-field carry/borrow/signed overflow, an intra-tile stencil, and an exact unsigned+signed fold. Four realizations (u128, SoA U64x8, widened U32x16, bit planes over full_add_mask) are checked against one unpacked oracle on six SIMD realizations, with disable runs D1-D13. No realization wins every case; report in .claude/knowledge/microtile-probe.md. NEON/wasm U32x16 facade gaps recorded, not fixed. No public type, no backend change. Co-Authored-By: Claude Opus 5.5 <[email protected]> Claude-Session: https://claude.ai/code/session_01XAqKMPh2Seh2WLccCksAdY
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| for (ak, bk) in pa[j].chunks_exact(w).zip(pb[j].chunks_exact(w)) { | ||
| acc ^= planes_add(ak, bk, &mut op); |
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In the release cost gate, every bit-plane block writes its sum into the same op scratch buffer, but that buffer is never read; only the carry masks reach black_box. Because planes_add is inlined, the optimizer can eliminate the sum calculations and stores, leaving a carry-only benchmark. Even without that optimization, this path avoids writing a complete result dataset, unlike the other three addition paths. This makes the reported addition timings and bandwidth conclusions incomparable. Store each block's sum in a full output buffer and pass that output through black_box inside the timed closure.
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Step 1 of the micro/macro sequence in synergy map R7.6: a packed 128-bit microtile, checked against an exact oracle. This is a lab fixture. It adds no public type, changes no backend and has no production caller. Steps 2–4 (binding to a KPEA method, reusing Thought-0 work across thought deltas, interlacing) are not started.
What it is
The fixture is
examples/microtile/(four realizations plus a cost gate) andtests/microtile.rs(exactness). One 128-bit tile holds one of two layouts:Operations:
f[j-1] + 2f[j] + f[j+1];Every result keeps the left operand's metadata.
Realizations
All four are checked against one unpacked per-field oracle:
U64x8: 8 tiles per operation, each tile split into a low and a high 64-bit word. The fields that cross bit 64 get an explicit carry or borrow out of bit 63, computed with lane-wise logic only.U32x16: one field peru32lane. The fold flushes the lanes tou64before they can overflow.simd::full_add_mask, folded by popcount.Tests
core::simd.-D warnings, v3 and v4) and fmt are clean, and the FACET STRIDE guard passes.Cost gate
x86 only; ns per tile, as the range across three runs. Full table in
.claude/knowledge/microtile-probe.md. No realization wins every case:Found along the way
On NEON and wasm,
U32x16lacks&,|,-,!,+=,from_sliceandcopy_to_slice. The fixture works around this; the gap is recorded in the report, not fixed here.No automatic merge.
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