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@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.3k 962

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 447 152

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 101 40

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 189 111

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 76

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 352 146

Repositories

Showing 10 of 110 repositories
  • GEM5 Public
    OpenXiangShan/GEM5's past year of commit activity
    C++ 166 BSD-3-Clause 96 18 107 Updated Oct 15, 2026
  • XiangShan-doc Public

    Documentation for XiangShan

    OpenXiangShan/XiangShan-doc's past year of commit activity
    Markdown 447 CC-BY-4.0 152 7 0 Updated Oct 15, 2026
  • bootcamp Public

    XiangShan bootcamp

    OpenXiangShan/bootcamp's past year of commit activity
    Jupyter Notebook 7 CC-BY-4.0 4 0 0 Updated Oct 15, 2026
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 352 146 40 44 Updated Oct 15, 2026
  • XiangShan-Design-Doc Public

    Documentation for XiangShan Design

    OpenXiangShan/XiangShan-Design-Doc's past year of commit activity
    Markdown 52 CC-BY-4.0 17 5 8 Updated Oct 15, 2026
  • difftest Public

    Modern co-simulation framework for RISC-V CPUs

    OpenXiangShan/difftest's past year of commit activity
    C++ 189 MulanPSL-2.0 111 8 4 Updated Oct 15, 2026
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,312 MulanPSL-2.0 962 143 181 Updated Oct 15, 2026
  • env-scripts Public

    Scripts for XiangShan

    OpenXiangShan/env-scripts's past year of commit activity
    Tcl 18 23 0 9 Updated Oct 15, 2026
  • XiangShanLab Public

    XiangShanLab is the open-source XiangShan ecosystem's entry layer — a learning, practice, and collaboration hub spanning the RISC-V processor core and its specialized domains, making high-performance processor design learnable, doable, and participable, and welcoming collaborators from academia and industry to join real open-source development.

    OpenXiangShan/XiangShanLab's past year of commit activity
    Scala 51 26 55 2 Updated Oct 15, 2026
  • XSCache Public

    Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.

    OpenXiangShan/XSCache's past year of commit activity
    Scala 3 8 0 7 Updated Oct 15, 2026