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[mailbox,dv] Add the testplan, vPlan skeleton and register description - #756
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Describe the registers of the vendored PULP axi_lite_mailbox for the Mocha instance, from its documentation. ralgen builds the UVM register model from it, and the CSR tests check it against the hand-written RTL. Signed-off-by: Martin Velay <[email protected]>
The testplan lists the V1 and V2 testpoints. The vPlan names the features to verify with their references and milestones, and gets its coverage items once the environment exists. Signed-off-by: Martin Velay <[email protected]>
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First part of the mailbox block-level DV (#173): the plan and the register description. The UVM environment comes in later commits, built on the AXI agent from #688.
hw/top_chip/dv/mailbox/data/mailbox.hjsondescribes the registers of the vendored PULPaxi_lite_mailboxfor the Mocha instance (AxiDataWidth64,MailboxDepth3), written fromhw/vendor/pulp_axi/doc/axi_lite_mailbox.md. It is only used to generate the UVM register model with ralgen. The RTL registers are hand-written, so the CSR tests are what keep the two aligned.mailbox_testplan.hjsonholds the V1 and V2 testpoints.mailbox_vplan.hjsonis a skeleton: features, references and milestones, with no coverage items yet.The registers are 64 bits wide, so the sim cfg will have to set
tl_dwto 64 andtl_dbwto 8. With the default of 32, UVM stops atlock_model().Open questions on the specification are in #755, and the IRQS reset bug is #754.